This invention relates to an image processing apparatus and method as well as a providing medium, and more particularly to an image processing apparatus and method as well as a providing medium by which a picture size and a vertical frequency of a video signal can be converted while suppressing line flickering without deterioration of a vertical resolution.
Television broadcasting in Japan is-based on the NTSC color TV system, and television receivers in Japan are usually designed so as to receive and display an interlaced video signal (525i) having 525 scanning lines. Meanwhile, also television receivers which can display an interlaced video signal of 625i of the PAL system, an interlaced video signal of 1080i used for high definition television broadcasting and a non-interlaced video signal of 525p for displaying line sequentially 525 scanning lines begin to be put on the market. If any of video signals of 525i, 625i, 525p and 1080i is inputted to a television receiver of the type mentioned, the television receiver converts the inputted video signal into and displays an image of a predetermined size of a predetermined unified frequency. The unified frequency may be, for example, 525p. In this instance, the horizontal scanning frequency fh is 31 kHz, and the field (frame) frequency fv is 60 Hz.
FIG. 9 shows an example of a configuration of a conventional television receiver of the type described above. Referring to FIG. 9, an A/D converter 1 converts analog video signals Yi1, Ui1 and Vi1 of a first frequency inputted to the television receiver into digital signals and outputs the digital signals to a low-pass filter (LPF) 2. The LPF 2 extracts only predetermined low frequency components from horizontal and vertical frequency components of the signals inputted thereto and outputs the extracted low frequency components to an interpolation circuit 3. The interpolation circuit 3 reduces the image data inputted thereto from the LPF 2 by interpolation calculation and supplies the reduced video signals to a frame memory 4. Writing and reading operations of the frame memory 4 are controlled by a write memory controller 5 and a read memory controller 6, respectively. Another interpolation circuit 7 converts data read out from the frame memory 4 into video data of a greater screen and outputs the resulting video data to a mixing (Mix) circuit 15.
Processes similar to those performed by the components from the A/D converter 1 to the interpolation circuit 7 are performed also for other video signals Yi2, Ui2 and Vi2 by a different set of components from an A/D converter 8 to another interpolation circuit 14 which are similar to the components from the A/D converter 1 to the interpolation circuit 7, respectively.
The mixing circuit 15 selects outputs of the interpolation circuit 7 or outputs of the interpolation circuit 14 and outputs the selected outputs to a D/A converter 16. The D/A converter 16 converts the video signals inputted thereto in the form of digital signals into analog signals and outputs the analog signals to a display unit such as a cathode ray tube (CRT) not shown.
In operation, the A/D converter 1 converts analog signals inputted thereto into digital signals and outputs the digital signals to the LPF 2. The LPF 2 extracts predetermined low frequency components of the inputted video signals and outputs the low frequency components to the interpolation circuit 3. The interpolation circuit 3 performs a reduction process by linear interpolation if it is required to reduce the inputted video signals, and supplies the reduced video signals to the frame memory 4 so that they may be stored into the frame memory 4. The write memory controller 5 controls the writing process of the reduced video signals into the frame memory 4.
The video signals stored in the frame memory 4 are read out under the control of the read memory controller 6 and supplied to the interpolation circuit 7. The interpolation circuit 7 processes the video signals read out from the frame memory 4 to expand the size of a screen by interpolation processing when necessary, and outputs the video signals of the expanded screen size to the mixing circuit 15.
Similar processing is performed also by the components from the A/D converter 8 to the interpolation circuit 14, and resulting video signals are supplied to the mixing circuit 15.
The mixing circuit 15 selects the video signals inputted from the interpolation circuit 7 or the video signals inputted from the interpolation circuit 14 and outputs the selected video signals to the D/A converter 16. The D/A converter 16 converts the video signals in the form of digital signals into analog signals and outputs the analog signals to the CRT or the like display unit not shown.
The television receiver thus converts, for example, video signals of 1080i, video signals of 525i or video signals of 625i into video signals of 525p in regard to the screen size and the number of scanning lines as seen in FIG. 10 so that the video signal of 525p may be displayed.
FIG. 11 shows an example of a more detailed configuration of a portion of the television receiver shown in FIG. 9 which includes the frame memory 4, write memory controller 5 and read memory controller 6 described above. A digital video signal outputted from the interpolation circuit 3 is inputted to a field memory 34 and a field memory 35 which correspond to the frame memory 4. Also a write side memory control signal (for example, an enable signal) supplied from a circuit not shown is supplied to the field memory 34 and the field memory 35. A switch 33 is switchable to a contact xe2x80x9caxe2x80x9d side or a contact xe2x80x9cbxe2x80x9d side in response to the write side field switching signal supplied thereto from a circuit not shown.
Also a read side memory control signal (enable signal) is supplied to the field memory 34 and the field memory 35 through another switch 37. The switch 37 is switchable to a contact xe2x80x9caxe2x80x9d side or a contact xe2x80x9cbxe2x80x9d side in response to the read side field switching signal outputted from a D-type flip-flop 32. Also a further switch 36 is switchable to a contact xe2x80x9caxe2x80x9d side or a contact xe2x80x9cbxe2x80x9d side in response to the read side field switching signal and outputs a vide signal read out from the field memory 34 or the field memory 35 to the interpolation circuit 7.
The D-type flip-flop 32 latches the write side field switching signal in response to a read side readout start pulse detected by and outputted from a start position detection circuit 31 and outputs the latched write side field switching signal as a read side field switching signal to the switch 36 and the switch 37.
Operation of the circuit shown in FIG. 11 is described with additional reference to time charts of FIGS. 12A through 12E.
The switch 33 is switched to the contact xe2x80x9caxe2x80x9d side in response to a level change of the write side field switching signal (FIG. 12B) to the high level, but switched to the contact xe2x80x9cbxe2x80x9d side in response to a level change of the write side field switching signal to the low level. A write side line address count signal (FIG. 12A) is supplied to the field memory 34 when the write side field switching signal (FIG. 12B) has the high level, but is supplied to the field memory 35 when the write side field switching signal has the low level. As a result, a digital video signal supplied from the interpolation circuit 3 is written into the field memory 34 when the write side field switching signal (FIG. 12B) has the high level, but is written into the field memory 35 when the write side field switching signal has the low level.
On the other hand, the write side field switching signal (FIG. 12B) is latched by the D-type flip-flop 32 in synchronism with a read side readout start pulse (FIG. 12D) outputted from the start position detection circuit 31 and is supplied as a read side field switching signal (FIG. 12E) to the switch 36 and the switch 37. The switch 36 and the switch 37 are switched to the contact xe2x80x9cbxe2x80x9d side when the read side field switching signal (FIG. 12E) has the high level, but are switched to the contact xe2x80x9caxe2x80x9d side when the read side field switching signal (FIG. 12E) has the low level. A read side line address count signal (FIG. 12C) is supplied to the field memory 35 when the read side field switching signal (FIG. 12E) has the high level. As a result, a video signal read out from the field memory 35 is supplied to the interpolation circuit 7 through the contact xe2x80x9cbxe2x80x9d of the switch 36.
Similarly, when the read side field switching signal (FIG. 12E) has the low level, the read side line address count signal (FIG. 12C) is supplied to the field memory 34. Consequently, a video signal read out from the field memory 34 is supplied to the interpolation circuit 7 through the contact xe2x80x9caxe2x80x9d of the switch 36.
In this manner, in the circuit shown in FIG. 11, for example, in order to convert an interlaced video signal of 625i (fh=15 kHz, fv=50 Hz) into a non-interlaced signal of 525p (fh=31 kHz, fv=60 Hz), one field processing is performed in order to prevent line flickering from being observed conspicuously on a display screen. In particular, upon writing, when an odd-numbered field of an nth frame is written into the field memory 34, a video signal of an odd-numbered field of the next n+1th frame is written into the field memory 35.
Similarly, when an interlaced signal of 525i (fh=15.734 kHz, fv=60 Hz) or 625i (fh=15.625 kHz, fv=50 Hz) is set as a video signal to be outputted, where the input signal is a video signal of 625i or 525i, since vertical frequency conversion is involved, one field processing is performed in order to prevent line flickering from being observed conspicuously on a display screen.
However, where one field processing is performed in this manner, an image signal of one of an odd-numbered field and an even-numbered field is utilized from the image data of the two fields, and this results in deterioration of the vertical resolution. As a result, for example, an oblique straight line is displayed not as a smooth straight line but as a notched uneven line.
Also it is a possible idea to perform both field processing in place of one field processing. However, both field processing gives rise to a phenomenon wherein line flickering is observed conspicuously on a display screen.
In particular, when conversion of a vertical frequency, for example, from 60 Hz into 50 Hz is involved, if it is tried to perform the conversion so that fields of 60 Hz may correspond in a one-by-one corresponding relationship to fields of 50 Hz, a so-called passing phenomenon wherein a video signal of each field is displayed at a time later than a time at which it should originally be displayed occurs due to the difference in frequency.
In order to prevent such passing, for example, the same field is repetitively outputted periodically as seen from FIG. 14. In the outputting manner shown in FIG. 14, a video signal of the same field is outputted twice successively for each 6 fields. This particularly makes line flickering appear conspicuously on a display screen.
More particularly, in such a case that all of pixels of five lines from the first to fifth of an odd-numbered field are black and all pixels of lines below the fifth line are white as seen in FIG. 15, since a line of an even-numbered field is positioned between lines of the odd-numbered field, the pixels of the four lines from the first to the fourth are black and the pixels of the lines below them are white.
If the pixels of the lines of the odd-numbered field and the even-numbered field are used as pixels of lines of each field (frame) of the non-interlaced display, then the pixels of the five lines from above in the odd-numbered field are black, but the pixels of the four lines from above in the even-numbered field are black. As a result, when the images of the even-numbered field and the odd-numbered field are displayed alternately, then the black pixels and the white pixels of the same still image are displayed alternately on the fifth line from above. Such alternate display of the black pixels and the white pixels is observed as line flickering of the frequency of 30 Hz.
Although line flickering occurs also where no conversion of a vertical frequency is involved, where conversion of a vertical frequency is involved, line flickering appears particularly conspicuously because the frequency with which line flickering occurs is lower than that where conversion of a vertical frequency is not involved.
It is an object of the present invention to provide an image processing apparatus and method as well as a providing medium by which conspicuous appearance of line flickering can be suppressed without deterioration of the vertical resolution.
In order to attain the object described above, according to an aspect of the present invention, there is provided an image processing apparatus, comprising discrimination means for discriminating a relationship between a video signal inputted and a video signal to be outputted, supply means for supplying a predetermined initial value in response to a result of the discrimination of the discrimination means, generation means for generating a predetermined coefficient using the initial value supplied thereto from the supply means, and calculation means for calculating pixel data of the video signal to be outputted from pixel data of the inputted video signal using the coefficient generated by the generation means.
According to another aspect of the present invention, there is provided an image processing method, comprising a discrimination step of discriminating a relationship between a video signal inputted and a video signal to be outputted, a supply step of supplying a predetermined initial value in response to a result of the discrimination in the discrimination step, a generation step of generating a predetermined coefficient using the initial value supplied in the supply step, and a calculation step of calculating pixel data of the video signal to be outputted from pixel data of the inputted video signal using the coefficient generated in the generation step.
According to a further aspect of the present invention, there is provided a providing medium which provides a computer-readable program for causing an information processing apparatus to execute a process comprising the steps of a discrimination step of discriminating a relationship between a video signal inputted and a video signal to be outputted, a supply step of supplying a predetermined initial value in response to a result of the discrimination in the discrimination step, a generation step of generating a predetermined coefficient using the initial value supplied in the supply step, and a calculation step of calculating pixel data of the video signal to be outputted from pixel data of the inputted video signal using the coefficient generated in the generation step.
In the image processing apparatus, image processing method and providing medium, a coefficient is produced using an initial value produced based on a relationship between a video signal inputted and another video signal to be outputted, and pixel data of the video signal to be outputted are calculated from pixel data of the inputted video signal making use of the generated coefficient. Consequently, deterioration of the vertical resolution can be prevented by both-field processing, and line flickering can be suppressed from being observed conspicuously on a display screen.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements denoted by like reference symbols.